Synchronous digital design techniques are focused upon the definition of a stable clock reference signal that is used as a time-based reference with which data is propagated throughout a digital system. A clock distribution network is often utilized to distribute the stable clock reference signal from a common reference point, so that clock signal characteristics, such as clock skew and phase jitter, may be well understood and controlled.
Ideally, every logic change in each storage element of a synchronous digital design occurs simultaneously with the rising edge and/or falling edge of the clock signal. Storage elements, such as flip-flops and registers, are utilized to enforce the synchronous operation of the design, which also includes combinatorial logic. Depending upon the delay introduced by the combinatorial logic and other factors, hold-time and setup-time violations may be experienced. Thus, accurately controlling the timing at which each rising edge and/or falling edge of the clock signal occurs at each storage element is critical to the design's performance.
As such, synchronous circuit designers often design circuits that receive a reference clock signal, which then performs adaptation operations on the reference clock signal depending upon the needs of the particular clock domain of interest. In many instances, such clock signal adaptation includes clock division circuitry to reduce the frequency of the reference clock signal in the clock domain. Other clock signal adaptation operations include duty cycle correction, phase alignment, clock signal multiplication, and clock signal phase adjustments.
Clock signal adaptation circuits often include the use of phase-locked loops (PLLs), for example, to extract a 50% duty cycle clock signal from a pulse waveform. Similarly, phase alignment, clock signal multiplication, and clock signal phase adjustments may also be implemented through the use of a PLL. PLL design, however, relies substantially on analog design practices, which may increase simulation time and complexity. Furthermore, a PLL design that functions properly using a first integrated circuit (IC) topology may cease functioning properly when utilized with a second IC topology due to manufacturing process variations between the IC topologies.
Digital delay lock loops (DLLs) may also be utilized to perform similar clock signal adaptation functions, such as duty cycle correction and clock signal phase shifting. DLL circuit designs, however, are typically large and generally cannot be used in applications where the frequency of the input clock reference signal is unknown. Thus, duty cycle correction and phase shifting of the input clock reference signal may be impractical or even impossible using conventional circuit designs and methods.
Counter-based circuits, therefore, such as described in U.S. Pat. No. 6,788,120 issued on Sep. 7, 2004, to Nguyen (hereinafter “Nguyen '120”) may be utilized to provide duty cycle correction (DCC) on an incoming clock signal. The implementation described in Nguyen '120, however, requires two clock cycles to achieve DCC and, therefore, is unable to update DCC on each clock cycle of the incoming clock signal. Furthermore, the implementation described in Nguyen '120 does not maximize efficiency of logic usage, which increases the complexity of the design and increases power and semiconductor die area usage.
Similar counter-based circuits are described in U.S. Pat. No. 6,924,684 issued on Aug. 2, 2005, to Nguyen (hereinafter “Nguyen '684”) and U.S. Pat. No. 7,236,557 issued on Jun. 26, 2007, to Nguyen (hereinafter “Nguyen '557”) to implement phase-shifting and multiplication, respectively, of an incoming clock signal. The phase-shifter as described in Nguyen '684, however, is limited to phase shift multiples of ½ and requires a separate input signal to determine shift value. In addition, the implementation described in Nguyen '684 requires two clock cycles to achieve the required phase shift value and, therefore, is unable to update the requisite phase value on each clock cycle of the incoming clock signal. Furthermore, the implementation described in Nguyen '684 does not maximize efficiency of logic usage, which increases the complexity of the design and increases power and semiconductor die area usage.
The multiplier as described in Nguyen '557 exhibits similar limitations. For example, only certain even integers of multiplication, e.g., 2, 4, 8, 16 etc., are possible. In addition, the implementation described in Nguyen '557 requires two clock cycles to achieve the required multiplier value and, therefore, is unable to update the requisite multiplier value on each clock cycle of the incoming clock signal. Furthermore, the implementation described in Nguyen '557 does not maximize efficiency of logic usage, which increases the complexity of the design and increases power and semiconductor die area usage.
Efforts continue, therefore, to provide clock signal adaptation circuits that are based neither on PLL methodologies nor DLL methodologies and that improve conventional counter-based circuitry to achieve decreased complexity, increased versatility, decreased power consumption, and faster adaptation.